April 30, 2009
Completed a simple loadable Linux device driver that can read/write to the FPGA's BRAM. Next step is to create an device node interface (i.e. /dev/xc5vsx50t) so user-space applications can interact with the FPGA over PCIe.
April 1, 2009
Started researching the development of Linux kernel driver modules for PCIe using WinDriver. Good references are WinDriver's User's Manual, Low-level API Reference and Linux Loadable Kernel Module HOWTO. My first task is to build a simple driver that does single 32-bit integer read/write over PCIe using WinDriver.
December 11, 2008
We now have the PCIe + MicroBlaze design fully functional. What I will be working on next is a Windows device driver that will allow easy communication with the FPGA's resource over PCIe. This driver is necessary because Windows "protects" the system by disallowing direct access to the PCIe memory space by normal user-space applications. There were also a few questions brought up regarding the capabilities of PCIe on the FPGA.
Q: What FPGA resources can be access by the PC through PCIe?
A: Any peripheral connected to the PLBv46 bus. This list includes (but is not limited to):
- External SDRAM (mpmc)
- External SRAM (xps_mch_emc)
- SystemACE CompactFlash (xps_sysace)
- On-chip BRAM (xps_bram_if_cntlr)
- DMA Controller (xps_central_dma)
- Ethernet Controller (xps_ethernetlite)
- Partial Bitstream Reconfigurator (xps_hwicap)
- Any custom core we can create a PLBv46 bridge for
Q: Can the workstation reset the FPGA forcing it to reload its bitstream?
A: A workstation reboot will reset the FPGA because the PCIe reset pin is connected to the FPGA's reset pin. If the FPGA is configured to load its bitstream from CompactFlash, we could technically write a new bitstream to CompactFlash (via PCIe) and force the workstation to reboot. This will cause the FPGA to also reboot and load the new bitstream.
November 14, 2008
With the help of Matt I was able to figure out the address range allocated for the FPGA PCIe by Windows (look in Device Manager). Using this address range I'm now rebuilding the design with the correct Base Address Register (BAR) values. Hopefully this will allow us to successfully initiate memory transactions from the FPGA to PC. Will update once build is complete.
--Yoavfreund 00:40, 15 November 2008 (UTC) Excellent! I know from matt that the work on the PCIe has been slow and frustrating, but I think it is extremely important. Once we have this link we can start communicating between the FPGA board and the rest of the world, first the PC and then, through ethernet, other computers, this will be MAJOR. Don't give up!!!
October 25, 2008
Fixed the problem with PC not recognizing EDK based design (for some reason PCIe reset line is active low and not active high). Now working on C program for MicroBlaze to initiate a DMA transfer from FPGA's BRAM to PC's memory over the PCIe.
--Yoavfreund 01:02, 26 October 2008 (UTC) Excellent! I am excited!
October 24, 2008
I was able to successfully initiate memory reads and writes from the PC to the FPGA BRAM through the PCIe interface (verified using PCItree software). I did this using the standalone Endpoint Block Plus Wrapper for PCI Express and not the EDK based design (still having problems getting the PC to properly initialize using the EDK based design). I'm going to work on getting the FPGA to initiate memory transactions to the PC which is much simpler to do using the EDK based design.
October 20, 2008
Researched how memory segments are mapped between PCIe's memory space and the FPGA's memory space using. See plbv46_pcie.pdf under the Address Translation section. Completed the EDK project for simple PCIe transmissions over the PLBv46 bus. Next step is to write a small C program to initiate PCIe transmissions in order to test the bitstream.
October 16, 2008
Created MSS and MHS files for PCIe endpoint project in EDK. These files map the physical pins of the PCIe to logical wires in the design. A useful reference was the ML506 UCF Pin Constraints and XAPP1030 Reference System. I'm still unsure about how to actually map BlockRAM addresses to be PCIe addressable using Base Address Register (BAR) configurations.
October 15, 2008
Started building the PCIe endpoint project in EDK. This project integrates MicroBlaze, PCIe endpoint core, PLB to PCIe bridge and DMA cores (the system will look something like the diagram below). Also installed PCItree in preparation for testing the PCIe endpoint.
October 10, 2008
Began work on creating custom PIO for driving data to the PC (see PCIExpressPIO).
October 3, 2008
I was able to get CORE generator to generate a fully licensed version of the PCIe endpoint block. The IP core generated and synthesized correctly. I also researched into how the PCIe endpoint core functioned and what needs to be done to implement user logic and found this, Programmed Input Output (PIO) Reference Design. The next step is to create (or modify) our own PIO to drive high-speed data transfers.