MEM FPGA DESIGN
Documentation of the FPGA and PCIe code that Sameh and Patrick developed for capturing the signals from the MEM microphone.
The files are organized in two top directories:
Hardware directory: ML507_PCIe
The EDK project http://seed.ucsd.edu/~sittarpa/ML507_PCIe_MEM_Project.zip contains the complete design
This folder contains :
- Base system builder of the Mem microphone project for the XILINX ML507 Board
- The folder MyProcessorIPLib which contains the IP Core of MIC.(see next section MyProcessorIPLib)
This EDK project allows the user to use one TC100E Pulse engineering microphone. The 1-bit PDM dataouput from this microphone are recorded into the BRAM Memory.
Note : The user can read the BRAM memory through the PCIe by using the driver which is in the "ML507_xcvfx70t_driver" folder ( see above).
- In EDK 11.2, Run in the menu : Device Configuration -> Download Bitstream. - When it's DONE, Reboot the computer so that BIOS MEMMicrophones#PCIe_Bus and OS can recognize the Board through the PCIe. - Then install the driver "ML507_xcvfx70t_driver" in order to communicate with the PCIe.
A sub-directory of ML507_PCIe.
An ISE 11.2 project containing the design of the core for capturing the TCL100E Pulse engineering microphone data.
This core is integrated into EDK using the Create and Import Peripheral Wizard using "create". The choices made during this import process are (EDK11.2 or 10.1):
- Default choices up to and including "Bus Interface"
- On Page "IPIF (IP Interface) Services, check "User Logic Memory Space"
- On Page "IP Interconnect" make sure all IPIC ports are checked.
- On "Peripheral implementation support" check "Generate stub 'user logic' ..."
(This creates a connection of the microphone pcore to the PLB bus as a slave (which can be removed). This is an over-design, we don't use the direct connection between the Mic core and the plb bus.)
When this process is completed, two verilog file stubs are created, these files are then expanded upon using ISE11 to implement the core. The stubs are: "hdl/vhdl/mic.vhd" which is the top level interface and "hdl/vhdl/user_logic.v" which holds the verilog for the core (this is the main design file), "data/mic_v2_1_0.mpd" which identifies for EDK the pins in the core that need to be visible to EDK.
In addition there is a file in the EDK project at "data/system.ucf" this file defines the FPGA pin assignments. To know which pins are assigned to which functions on the board, consult MEMMicrophones#Microphone_TC100E_Pins_Connexions
Hardware description files
/MEM_Project/ML507_PCIe/MyProcessorIPLib/pcores/mic_v1_00_a/hdl/verilog/user_logic.v: The main Verilog file of ip core MIC
/MEM_Project/ML507_PCIe/MyProcessorIPLib/pcores/mic_v1_00_a/hdl/vhdl/mic.vhd: The top level file of ip core MIC
/MEM_Project/ML507_PCIe/MyProcessorIPLib/pcores/data/mic_v2_1_0.mpd : The port parameter file of the ip core MIC
/MEM_Project/ML507_PCIe/data/system.ucf : The fpga pin connections file of the EDK project
Software directory : ML507_xcvfx70t_driver
The PC/Linux side software that communicates with the card through PCIe
- Go into the folder "ML507_xcvfx70t_driver" and type in a shell command this following command :
-- make clean -- make -- sudo make load
- To check if the driver module is well loaded into the kernel , use the following instruction here :  . If the driver is working, you can read and record into .txt file the content of the Bram memory by doing this command:
-- sudo ./Bram (if you modified the Read_Bram.c , don't forget to regenerate Bram : gcc Read_Bram.c -o Bram)
Software description files
This folder contains 3 files :
- /MEM_Project/ML507_xcvfx70t_driver/xc5vsx50t.c : driver from Patrick Lai (Modified by Sameh Ben Fredj and Patrick Sittaramane )
Some modification have to be made about the XILINX_VENDOR_ID and the XILINX_DEVICE_ID so that the driver can work correctly. Those modifications are required because P. Lai used the ML506 board and this code is for the ML507 board.
- /MEM_Project/ML507_xcvfx70t_driver/Test.c : read and write into the bram (Done by Patrick Lai)
- /MEM_Project/ML507_xcvfx70t_driver/Read_Bram.c : read and record the content of the Bran memory into a file (MEM.txt) (from Sameh Ben Fredj and Patrick Sittaramane)
- We found this code on internet in the Matlab exchange. We made some modifications on the parameters in order to plot the Data (16bits PDM to 16bits PCM) from the MEM.txt file. We also generates a audio.wav file
- In the text file you will see a table of values each value is like 'MEMdata' FF 'BITScounter'.
For example you will read 145dFF10 which means that 145d is the 16 bits PDM from microphone and 10 the counter value (here 0x10 = 16)
- Be sure to remove ff10 from the text file before using the matlab files
- This image below represents a data sequence from one address memory
Generating and integrating the dual-port BRAM
This is all done in EDK. It would make sense to connect the microphone pcore to the bram and the memory controller in ISE, but we did not manage to do this. As the import-peripheral wizard does not allow a core without a connection to the PLB bus, we end up with a PLB bus connection that we don't use.
To create the memory controller we go to the IP catalog in EDK and choose Memory and memory controller / XPS BRAM Controller this creates a memory controller that is connected to the PLB as a slave. This new core appears on the "bus interfaces".
The create the BRAM core we go back to the IP catalog and choose Memory and memory controller / Block RAM (BRAM) and adds that to the bus interfaces.
TO connect the controller to the BRAM choose the drop down menu of BRAM / PORT A and choose the name that was assigned by EDK to port A in the controller.
To choose the size of the BRAM go to the "Addresses" tab and select 64K for the size of "XPS_BRAM_IF_NTRLR_0". for full documentation about this controller look at the data sheet for the controller "XPS BRAM Interface Controller (V1.00a)". Then click "Generate Addresses" to create the base and high addresses.
Connecting the microphone core to the BRAM. The design of the microphone core exports the lines that are for connecting to the bram. These lines need to be connected to the other port of the BRAM. See the screenshot on the RHS.